fRSTL_stm32

The fRSTL_stm32 portfolio provides a simple means to detect and flag potentially dangerous failures in STM32-bit ARM Cortex MCUs. This means system manufacturers have the ability to reach the target safety integrity level with no or limited safety specific HW mechanisms integrated in the components.

The SW test Libraries are developed according to IEC 61508 2nd edition and each Safety Manual describes how they can be integrated in systems targeting other safety-related standards including ISO 13849-1, IEC 62061, IEC 61800-5-2, IEC 60730 and ISO 26262.

faultRobust technology

The comprehensive technology addressing functional safety according to multiple standards like IEC 61508, ISO 26262, ISO 13849, IEC 62061, IEC 61800-5-2, IEC 60730. Fault robustness is more than functional safety because it aims to
combine reliability, availability, security and safety. faultRobust® paradigm is to reach “as much fault tolerance as you need”, i.e. optimizing costs, power and performance impacts of the additional artifacts (safety analyses, safety verification, HW and SW safety mechanisms) needed to fulfill the requirements of functional safety standards with respect to both systematic and HW random failures.

 

Testimonials

YOGITECH's Analog Mixed Signal Verification Kit enabled us to reliably verify our Digital and Analog Mixed-Signal SoC's within in a unified environment that is familiar to the System on Chip verification engineers.
We have successfully validated complex analog interfaces (including power management) and IP applying exactly the same techniques and methods traditionally applied on their digital equivalents.
YOGITECH's automated, metrics-driven coverage methodology increased verification quality and accelerated the entire process.

Robin Wilson
Design Department Manager, Design for Qualification, STMicroelectronics

YOGITECH's OCP eVC, with its excellent documentation and support, proved to be effective and reliable in quickly verifying our core based ASICs.

Andreas Dieckmann
Verification Manager of Siemens AG

As OCP IP GSC Member (Governing Steering Committee) Texas Instruments has been a leading customer for the OCP eVC and has successfully adopted this verification tool in several key designs. We worked closely with YOGITECH as an early adopter of this product to get the best results improve and enable re-use of our verification platform.

Ziad Mansour
OMAP Hw Program Manager of Texas Instruments

The high verification quality of our OMAP platform has depended heavily on our use of the YOGITECH OCP eVerification Component.

Vincent Gillet
OMAP Verification Manager of Texas Instruments

YOGITECH has shown a strong commitment to both OCP-IP and our Functional Verification Working Group. Their tremendous work is a further illustration of the thriving robust infrastructure surrounding OCP and the tremendous support and adoption throughout the industry. We are grateful to YOGITECH for their contribution.

Ian Mackintosh
President of OCP-IP